-- $Id: $
-- File name:   EDGE_DETECT.vhd
-- Created:     10/5/2010
-- Author:      Christopher Sakalis
-- Lab Section: 4
-- Version:     1.0  Initial Design Entry
-- Description: Edge Dedector.


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

entity EDGE_DETECT is
    port( CLK : in std_logic;
        RST_N : in std_logic;
       D_PLUS : in std_logic;
       D_EDGE : out std_logic);
end EDGE_DETECT;



architecture BEHAVIORAL of EDGE_DETECT is
  signal oldBit: std_logic;
  signal NEXToldbit: std_logic;
  signal curr: std_logic;
  signal NEXTcurr: std_logic;
   Begin
     StateReg: process (CLK, RST_N)
      begin
        if (RST_N='0') then
          oldBit <= '1';
          curr <= '1';
        elsif (CLK'event and CLK='1') then
          oldBit <= NEXToldbit;
          curr <= NEXTcurr;
        end if;
     end process StateReg;

     NextReg: process(curr, D_PLUS)
     begin
--         NEXTcurr <= oldBit;
--         NEXToldBit <= D_PLUS;
        NEXTcurr <= D_PLUS;
        NEXToldBit <= curr;
     end process NextReg;
         --nextstate <= D_PLUS XNOR oldBit when SHIFT_ENABLE = '1'

      Out_cmp: process (curr, oldBit)
      begin
       D_EDGE <= curr xor oldBit;
     end process Out_cmp;

end BEHAVIORAL;



